1. Field of the Invention
The present invention relates to semiconductor electronic integrated circuits, and, more particularly, to integrated circuits made of III-V compound semiconductors including both field effect and bipolar devices.
2. Description of the Related Art
Microwave components and subsystems may be generally divided into two classes: (1) hybrid and (2) monolithic integrated circuit (MMIC). Hybrid technology permits combinations of varying device types, circuits on varying substrate types, and passive components that are not entirely compatible with the MMIC technology. The best use of hybrid technology arises when high performance is required from a given circuit. In this case discrete devices (of possibly various types) are chosen and screened to insure maximum performance, passive circuits are produced on low loss substrates, and after devices are connected to the circuits some tuning is applied to obtain the maximum performance for the resulting hybrid arrangement.
Conversely, MMIC technology is based on the use of only one type of device performing all of the circuits functions. The commonly used device type is the Schottky barrier gate GaAs field effect transistor (MESFET). The MESFET is flexible enough to be used in low noise amplifier, power amplifier, switch, mixer, doubler, and many other circuits. It performs most of these functions satisfactorily but none of them optimally. Other types of devices such as (high electron mobility transistors (HEMTs), heterojunction bipolar transistors (HBTs), and mixer diodes that can perform low noise, high power, or mixer functions better individually than MESFETs; but using one of these devices as only device type in MMIC circuits improves one function while degrading others. The performance degradation resulting from the nonoptimal use of active devices is partly offset by the monolithic integration of passive circuits and active devices. In addition, batch processing offered by MMIC technology improves circuit complexity and lowers fabrication cost.
Silicon digital circuits make use of vertical npn switching transistors as well as lateral pnp transistors for input logic, current sources and level shifting. The addition of junction field effect transistors (JFETs) with silicon bipolar transistors result in analog circuits which operate at high speeds while offering very high input impedences. The versatility of combining bipolar circuits and JFETs in a silicon integrated circuit is well known.
Historically GaAs/AlGaAs heterojunction bipolar transistors (HBT) have been fabricated using mesa technology in which the collector, base and emitter epi layers are sequentially grown during a single epitaxial deposition run. The emitter and base epi layer are selectively removed using two etch steps for making contact to the base and collector areas, respectively. These etches result in steps in the GaAs ranging in height between 0.4 and 1.0 micron for a typical mesa HBTs. See for example, K. Nagata et al, Self-Aligned AlGaAs/GaAs HBT with Low Emitter Resistance Utilizing InGaAs Cap Layer, 35 IEEE Tr.Elec.Dev. 2 (1988). Although high quality HBTs can be fabricated in this manner, the resulting mesa structure results in very severe topography making it difficult to incorporate a multilevel metal system as required for high levels of integration.
Planar heterojunction bipolar transistors have been fabricated as elements of integrated circuits in the emitter down configuration; see for example, L. Tran et al, GaAs/AlGaAs Heterojunction Emitter-Down Bipolar Transistors Fabricated on GaAs-on-Si Substrate, 8 IEEE Elec.Dev.Lett. 50 (1987). This avoids the mesa topography but has the drawbacks of limited npn base doping and limited multiple device integration possibilities. The deep base implant through the collector limits the base doping resulting in a high base sheet resistance and a "flat" doping profile. The integration possibilities have been explored in copending application Ser. No. 063,554, filed Jun. 18, 1987 (L. Tran) where an n-channel JFET was proposed with the npn. To integrate any more devices would require major changes in the epi and many additional processing steps. In addition, this technology requires all of the npn transistors to be connected in the common emitter configuration which severely limits its applications.
Although a single epitaxial deposition run as used in the mesa HBTs and emitter-down HBTs does simplify the fabrication process, it limits the types of structures which can be integrated together on a single chip.
U.S. Pat. No. 4,529,996 discloses and InP-BP heterojunction bipolar transistor in which a boron phosphide emitter is grown through an opening in a silicon dioxide mask on a indium phosphide substrate containing base and collector regions.
However, overgrowth methods have the drawbacks of not integrating multiple devices into the process and requiring spatially selective deposition of epitaxial layers. In the case of selective epi deposition, the epi material that falls on the silicon dioxide mask is wasted, and the selective epi process can lead to severe interface problems at the edges of openings in the silicon dioxide mask, resulting in regions of high stress and defect levels. The work of J. W. Tully, 7 IEEE Elec.Dev.Lett. 203 (1986) in emitter overgrowth onto an implanted base used Zn as a dopant because of the high mass and low implant range, however Zn diffuses rapidly in an uncontrolled manner at the temperatures needed for the second epi growth. Additional, Tully integrates only a single type of device, the npn HBT.
Thus the known MMIC methods have a problem of integrating GaAs MESFETs with HBTs.